Motorola MPC823e User Manual

System Interface Unit
MOTOROLA MPC823e REFERENCE MANUAL 12-5
SYSTEM INTERFACE UNIT
12
12.3 INTERRUPT CONFIGURATION
Many aspects of MPC823e system configuration are controlled by the SIU module
configuration register (SIUMCR). The SIUMCR primarily controls the external bus arbitration
logic, external master support, and pin multiplexing. See Section 12.12.1.1 SIU Module
Configuration Register for more information.
12.3.1 The Interrupt Structure
The system interface unit receives interrupts from internal sources, such as the periodic
interrupt timer, real-time clock, communication processor module (CPM), and the external
IRQx
pins. The MPC823e interrupt structure is illustrated in Figure 12-2.
If it is programmed to generate an interrupt, the software watchdog timer always generates
a nonmaskable interrupt (NMI) to the core. The external IRQ0
pin will generate a
nonmaskable interrupt as well.
Figure 12-2. MPC823e Interrupt Structure
LEVEL 2
LEVEL 7
LEVEL 6
LEVEL 5
LEVEL 4
LEVEL 3
LEVEL 1
LEVEL 0
NMI
IRQ[0:7]
IREQ
NMI
GEN
POWERPC
CORE
SYSTEM INTERFACE UNIT
TIMEBASE
PERIODIC
REAL-TIME
PCMCIA
CPM / LCD/VIDEO
SOFTWARE
IRQ0
INTERRUPT CONTROLLER
DECREMENTER
DECREMENTER
DEBUG
DEBUG
SELECTOR
EDGE
DET
INTERRUPT CONTROLLER
WATCHDOG
TIMER
INTERRUPT
TIMER
CLOCK

Motorola MPC823e Specifications

General

Brand	Motorola
Model	MPC823e
Category	Computer Hardware
Language	English