Memory Management Unit
MOTOROLA MPC823e REFERENCE MANUAL 11-33
MEMORY MANAGEMENT
11
UNIT
11.6.1.10 MMU INSTRUCTION TABLEWALK CONTROL REGISTER. The MMU
instruction tablewalk control (MI_TWC) register contains the access protection group and
page size of the entry to be loaded into the translation lookaside buffer.
Bits 0–22 and 30—Reserved
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read.
APG—Access Protection Group
A maximum of 16 protection groups are supported. The default value of instruction TLB miss
is 0.
G—Guarded Storage Attribute for Entry
Default value on instruction TLB miss is 0.
0 = Unguarded storage.
1 = Guarded storage.
PS—Page Size Level One
Default value on instruction TLB miss is 00.
00 = Small (4K or 16K).
01 = 512K.
11 = 8M.
10 = Reserved.
MI_TWC
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD RESERVED
RESET 0
R/W R/W
ADDR SPR 789
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD RESERVED APG G PS RES V
RESET 0———0—
R/W R/W R/W R/W R/W R/W R/W
ADDR SPR 789
NOTE: — = Undefined.
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