System Interface Unit
12-16 MPC823e REFERENCE MANUAL MOTOROLA
SYSTEM INTERFACE UNIT
12
TBREFL—Timebase Reference Lower
These bits represent the 32-bit reference value for the lower part of the timebase.
12.6.3 Timebase Status and Control Register
The 16-bit read/write timebase status and control register (TBSCR) controls the timebase
count enable and interrupt generation. It is also is used for reporting the source of the
interrupts and can be read at any time. A status bit is cleared by writing a 1 (writing a zero
has no effect) and more than one bit can be cleared at a time.
TBIRQ—Timebase Interrupt Request
This field determines the interrupt priority level of the timebase. To specify a certain level,
the appropriate bit must be set.
REFA and REFB—Reference Interrupt Status
If set, these bits indicate that a match has been detected between the corresponding
reference register (TBREFU for REFA and TBREFL for REFB) and the timebase low
register. Each bit must be cleared by writing a 1.
TBREFL
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD TBREFL
RESET —
R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0x208
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD TBREFL
RESET —
R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0x20A
NOTE: — = Undefined.
TBSCR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
TBIRQ REFA REFB RESERVED REFAE REFBE TBF TBE
RESET
0 00 0 0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x200
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