Motorola MPC823e - MMU Tablewalk Base Register

Memory Management Unit
11-36 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY MANAGEMENT
11
UNIT
11.6.1.12 MMU TABLEWALK BASE REGISTER. The MMU tablewalk base (M_TWB)
register contains a pointer to the level one table to be used in hardware-assisted tablewalk
mode.
L1TB—Tablewalk Level 1 Base Value
These bits are the most-significant bits of the level one pointer.
L1INDX—Level 1 Table Index
This field is ignored on write. It returns MD_EPN[0:9] on read when MD_CTR
TWAM
= 1 and
MD_EPN[2:11] when MD_CTR
TWAM
= 0.
Bits 30–31—Reserved
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read.
M_TWB
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD L1TB
RESET —
R/W R/W
ADDR SPR 796
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD L1TB L1INDX RESERVED
RESET ——0
R/W R/W R/W R/W
ADDR SPR 796
NOTE: — = Undefined.