Motorola MPC823e - The Condition Register

The PowerPC Core
6-22 MPC823e REFERENCE MANUAL MOTOROLA
CORE
6
DR—Data Relocate
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed.
Bits 28 and 29—Reserved
These bits are reserved and must be set to 0. Reserved bits in the MSR are set from the
source value on write and return the value last set for it on read.
RI—Recoverable Interrupt
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed.
LE—Little-Endian Mode
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed. This bit is loaded
from the ILE bit when an interrupt is taken.
6.4.1.2.2 The Condition Register. The condition register (CR) contains eight 4-bit
condition fields. Each field can have one of the following formats and the software can
assign an arbitrary meaning to them.
• Bit 0—Negative (LT). The result is negative.
• Bit 1—Positive (GT). The result is positive.
• Bit 2—Zero (EQ). The result is zero.
• Bit 3—Summary Overflow (SO). The values of this bit is copied from XER
SO
.