PowerPC Architecture Compliance
MOTOROLA MPC823e REFERENCE MANUAL 7-17
PPC ARCHITECTURE
7
COMPLIANCE
7.3.7.4 PARTIALLY EXECUTED INSTRUCTIONS. In general, the architecture allows
instructions to be partially executed when an alignment or data storage interrupt occurs. In
the core, instructions are not executed if an alignment interrupt condition is detected or if a
data storage interrupt is never generated by the hardware. In the MPC823e, the instruction
can be partially executed only in the case of load/store instructions that cause multiple
access to the memory subsystem—multiple/string and unaligned load/store instructions.
In this instance, the instruction can be partially completed if one of the accesses (except the
first one) causes a miss in the data TLB. The implementation-specific data TLB miss
interrupt is taken in this case. For the update forms, the update register (RA) is not altered.
7.3.8 Timer Facilities
Descriptions of the timebase and decrementer registers can be found in
Section 12 System Interface Unit and Section 5 Clocks and Power Control.
7.3.9 Optional Facilities and Instructions
Any other
PowerPC
Operating Environment Architecture (Book III)
optional facilities and
instructions that are not discussed here are not implemented by the MPC823e hardware.
Any attempt to execute any of these instructions causes an implementation-dependent
software emulation interrupt to occur.
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