Motorola MPC823e - Physical Location of Special Registers

The PowerPC Core
MOTOROLA MPC823e REFERENCE MANUAL 6-19
CORE
6
6.4.1.1 PHYSICAL LOCATION OF SPECIAL REGISTERS
Some of the special registers in the core are physically located outside of the core. Access
to these registers is gained the same way as any other special register—via the appropriate
mtspr, mfspr instructions through the internal chip buses. Apart from the PowerPC
timebase counter and decrementer, in the current implementation the following encoding is
reserved for special registers not located within the core.
For these registers, a bus cycle is performed on the internal bus with the following address.
If any address error occurs on this cycle, an implementation-dependent software emulation
interrupt is taken.
Table 6-10. Other Control Registers
DESCRIPTION NAME COMMENTS PRIVILEGED SERIALIZE ACCESS
Machine State Register MSR — Yes Write Fetch Sync
Condition Register CR — No Only mtcrf
Table 6-11. Encoding Special Registers Located Outside the Core
SPR RESERVED FOR
SPR
5:9
SPR
0:4
100xx 110xx xxxxx Registers External to the Core
1x0xx x0xxx Reserved
10011 x0xxx System Interface Unit Internal Registers
0xxxx xxxxx The Internal Bus Signifying Decrementer or Timebase
10000 x0xxx Reserved
10000 x1xxx Reserved
1100x x0xxx Instruction Memory Management Unit Implementation-Specific Control
1100x x1xxx Data Memory Management Unit Implementation-Specific Control
10001 x00xx Instruction Cache Registers
10001 x10xx Data Cache Registers
0:17 18:22 23:27 28:31
0. .0 spr
0:4
spr
5:9
0000