Reset
4-12
MPC823e REFERENCE MANUAL
MOTOROLA
RESET
4
DBPC—Debug Port Pins Configuration
This field configures the following pins on the active development port.
00 = ALE_B/DSCK/AT1 functions as defined by DBGC.
IP_B6/DSDI/AT0 functions as defined by DBGC.
OP3/MODCK2/DSDO functions as defined by DBGC.
IP_B7/PTR
/AT3 functions as defined by DBGC.
TCK/DSCK functions as DSCK.
TDI/DSDI functions as DSDI.
TDO/DSDO functions as DSDO.
01 = ALE_B/DSCK/AT1 functions as defined by DBGC.
IP_B6/DSDI/AT0 functions as defined by DBGC.
OP3/MODCK2/DSDO functions as defined by DBGC.
IP_B7/PTR
/AT3 functions as defined by DBGC.
TCK/DSCK functions as TCK.
TDI/DSDI functions as TDI.
TDO/DSDO functions as TDO.
10 = Reserved.
11 = ALE_B/DSCK/AT1 functions as DSCK.
IP_B6/DSDI/AT0 functions as DSDI.
OP3/MODCK2/DSDO functions as DSDO.
IP_B7/PTR
/AT3 functions as PTR.
TCK/DSCK functions as TCK.
TDI/DSDI functions as TDI.
TDO/DSDO functions as TDO.
EBDF—External Bus Division Factor
These bits define the frequency division factor between GCLK1/GCLK2 and
GCLK1_50/GCLK2_50. CLKOUT is similar to GCLK2_50. GCLK2_50 and GCLK1_50 are
used by the system interface unit and memory controller to interface with the external
system. The EBDF bits (described in
Section 5.2.1 System Clock and Reset Control
Register
) are initialized during HRESET
using the hard reset configuration mechanism.
4.3.2 Soft Reset
When a soft reset event occurs, the MPC823e reconfigures the development port.
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