PowerPC Architecture Compliance
7-2
MPC823e REFERENCE MANUAL
MOTOROLA
PPC ARCHITECTURE
7
COMPLIANCE
7.1.4 Exceptions
Invocation of the system software for any exception caused by an instruction in the core is
precise, regardless of the type and setting.
7.1.5 The Branch Processor
7.1.6 Fetching Instructions
The core fetches a number of instructions into its internal buffer (the instruction prefetch
queue) prior to execution. If a program modifies the instructions it intends to execute, it must
call a system library program to ensure that the modifications are visible to the instruction
fetching mechanism prior to executing the modified instructions.
7.1.7 Branch Instructions
The core implements all the instructions defined for the branch processor by the
PowerPC
User Instruction Set Architecture (Book I)
in the hardware. For details about the performance
of various instructions, see Table 8-1 of this manual.
7.1.7.1 INVALID BRANCH INSTRUCTION FORMS.
Bits marked with
z
in the BO
encoding definition are discarded by the core decoding. Thus, these types of invalid form
instructions yield results of the defined instructions with the
z
bit zero. If the decrement and
test CTR option is specified for the
bcctr
or
bcctrl
instructions, the target address of the
branch is the new value of the CTR. Condition is evaluated correctly, including the value of
the counter after decrement.
7.1.7.2 BRANCH PREDICTION.
The core uses the
y
bit to predict path for prefetch.
Prediction is only done for not-ready branch conditions. No prediction is done for branches
to the link or count register if the target address is not ready (see Table 6-1 for more details).
7.1.8 The Fixed-Point Processor
The core implements the following fixed-point instructions:
• Arithmetic instructions
• Compare instructions
• Trap instructions
• Logical instructions
• Rotate and shift instructions
• Move to/from system register instructions
All hardware instructions are defined for the fixed-point processor in the
PowerPC User
Instruction Set Architecture (Book I)
. For details about the performance of the various
instructions, see Table 8-1 of this manual.
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