Motorola MPC823e

Data Cache
10-12 MPC823e REFERENCE MANUAL MOTOROLA
DATA CACHE
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10.4.2.2 WRITETHROUGH MODE. In writethrough mode, store operations always update
memory. This mode is used when external memory and internal cache images must agree.
It gives a lower worst-case interrupt latency at the expense of average performance (for
example, if it does not have to do flush accesses). The possible outcomes of a data cache
write in writethrough mode are:
• Write Hit—Data is written into both the cache and memory, but the cache state is not
changed. The LRU of the set is updated to point to the way holding the hit data. If a bus
error is detected during the write cycle, the cache is still updated and a machine check
interrupt is generated.
• Write Miss—Data is only written into memory, not to the cache (write no allocate) and
no state transition occurs. The LRU is not changed, but if a bus error is detected during
the write cycle, a machine check interrupt is generated.
10.4.3 Data Cache Inhibited Accesses
If the cache access is to a page that has the CI bit set in the memory management unit, one
of the following outcomes will occur:
• Hit to Modified or Unmodified Line—This is considered a programming error if the
targeted location copy of a load, store, or dcbz instruction to cache inhibit storage is in
the cache. The result is boundedly undefined.
• Read Miss—Data is read from memory, but not placed in the cache. The cache’s status
is unaffected.
• Write Miss—Data is written through to memory, but not placed in the cache. The
cache’s status is unaffected.
10.4.4 Data Cache Freeze
The MPC823e can be debugged either in debug mode or by a software monitor debugger.
In both cases, the MPC823e core asserts the internal FRZ signal. For a detailed description
of MPC823e debug support, refer to Section 20 Development Capabilities and
Interface. When FRZ is asserted, the possible outcomes are:
• Read Miss—Data is read from memory, but not placed in the cache. The cache’s status
is unaffected.
• Read Hit—Data is read from the cache, but LRU is not updated.
• Write Miss/Hit—Data cache operates in writethrough mode, but LRU is not updated.
• dcbz Instruction Miss/Hit—Data is written into cache and memory, but LRU is not
updated.
• dcbst/dcbf/dcbi Instructions—The data cache and memory is updated according to
the PowerPC architecture, but LRU is not updated.