System Interface Unit
12-10
MPC823e REFERENCE MANUAL
MOTOROLA
SYSTEM INTERFACE UNIT
12
Bits 16–31—Reserved
These bits are reserved and must be set to 0.
12.3.3.4 SIU INTERRUPT VECTOR REGISTER.
The 32-bit read-only SIU interrupt vector
(SIVEC) register contains an 8-bit code that represents the unmasked interrupt source of
the highest priority level. The SIVEC register can be read as either a byte, half, or word.
When read as a byte, a branch table can be used in which each entry contains one
instruction (branch). When read as a half-word, each entry can contain a full routine of 256
instructions (max). The interrupt code is equal to the interrupt number multiplied by four,
which allows indexing into the table. Refer to Figure 12-3 and Table 12-1 for details.
INTC—Interrupt Code
This field indicates the highest priority pending interrupt.
Bits 8–31—Reserved
These bits are reserved and must be set to 0. The value equals the interrupt number
multiplied by four. See Table 12-1 for details.
SIVEC
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
INTC RESERVED
RESET
00
R/W
RR
ADDR
(IMMR & 0xFFFF0000) + 0x01C
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
RESERVED
RESET
0
R/W
R
ADDR
(IMMR & 0xFFFF0000) + 0x01E
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