Motorola MPC823e

The PowerPC Core
6-28 MPC823e REFERENCE MANUAL MOTOROLA
CORE
6
6.6.6 Executing Unaligned Instructions
The load/store unit supports fixed-point unaligned accesses in the hardware. The 32-bit
L-bus only supports naturally aligned transfers. For an unaligned instruction, the load/store
unit breaks the instruction into a series of aligned transfers that are pipelined into the bus.
Figure 6-7 illustrates the number of bus cycles needed to execute unaligned instructions.
00’h 00 01 02 03 1 BUS CYCLE
04’h 04 05 06 07
00’h 00 01
02 03 1 BUS CYCLE
04’h 04 05 06 07
00’h
00 01 02 03 1 BUS CYCLE
04’h 04 05 06 07
00’h 00
01 02 03 2 BUS CYCLES
04’h 04 05 06 07
00’h 00 01 02
03 2 BUS CYCLES
04’h 04 05 06 07
00’h 00 01
02 03 2 BUS CYCLES
04’h 04 05 06 07
00’h 00
01 02 03 3 BUS CYCLES
04’h 04 05 06 07
00’h 00 01 02
03 3 BUS CYCLES
04’h 04 05 06 07
Figure 6-7. Number of Bus Cycles Needed For Unaligned,
Single Register Fixed-Point Load/Store Instructions