System Interface Unit
12-36 MPC823e REFERENCE MANUAL MOTOROLA
SYSTEM INTERFACE UNIT
12
SWF—Software Watchdog Freeze
0 = The software watchdog timer continues counting even if the FRZ signal is
asserted.
1 = The software watchdog timer stops counting when the FRZ signal is asserted.
SWE—Software Watchdog Enable
This bit enables the software watchdog timer. To disable the software watchdog timer, it
must be cleared by the software after a system reset.
SWRI—Software Watchdog Reset/Interrupt Select
0 = The software watchdog timer causes a nonmaskable interrupt to the core.
1 = The software watchdog timer causes a system reset (default).
SWP—Software Watchdog Prescale
0 = The software watchdog timer is not prescaled.
1 = The software watchdog timer is prescaled by a factor of 2,048.
12.12.1.4 TRANSFER ERROR STATUS REGISTER. The transfer error status register
(TESR) contains a bit for each exception source generated by a transfer error. A bit set to
logic 1 indicates what type of transfer error exception occurred since the last time the bits
were cleared. The bits are cleared by reset or by writing a 1 to the appropriate bit. Canceled
speculative accesses that do not cause an interrupt may set these bits. The register has two
identical sets of fields–one is associated with instruction transfers and the other with data
transfers.
Bits 0–17 and 24–25—Reserved
These bits are reserved and must be set to 0.
TESR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
RESERVED
RESET
0
R/W
R
ADDR (IMMR & 0xFFFF0000) + 0x020
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
RESERVED IEXT ITMT IPB0 IPB1 IPB2 IPB3 RESERVED DEXT DTMT DPB0 DPB1 DPB2 DPB3
RESET
0 000000 0 000000
R/W
R RRRRRR R RRRRRR
ADDR (IMMR & 0xFFFF0000) + 0x022
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