Motorola MPC823e - MMU Instruction Effective Page Number Register

Memory Management Unit
MOTOROLA MPC823e REFERENCE MANUAL 11-19
MEMORY MANAGEMENT
11
UNIT
11.6.1.4 MMU INSTRUCTION EFFECTIVE PAGE NUMBER REGISTER. The MMU
instruction effective page number (MI_EPN) register contains the effective address to be
loaded into a TLB entry.
EPN—Effective Page Number for the TLB Entry
This field is the effective address default value of the last instruction TLB miss.
Bits 20–21 and 23–27—Reserved
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read.
EV—TLB Entry Valid Bit
This bit is set to 1 on every instruction TLB miss.
0 = The TLB entry is invalid.
1 = The TLB entry is valid.
ASID—Address Space ID
This field represent the address space ID of the instruction TLB entry to be compared with
the CASID field of the M_CASID register.
MI_EPN
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD EPN
RESET 0
R/W R/W
ADDR SPR 787
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD EPN RESERVED EV RESERVED ASID
RESET ——0 0 0
R/W R/W R R/W R R/W
ADDR SPR 787
NOTE: — = Undefined.