Motorola MPC823e

Instruction Cache
9-4 MPC823e REFERENCE MANUAL MOTOROLA
INSTRUCTION CACHE
9
9.2 PROGRAMMING THE INSTRUCTION CACHE
Three special-purpose registers can be used to control the instruction cache with the mfspr
and mtspr instructions:
• Instruction cache control and status register (IC_CST)
• Instruction cache address register (IC_ADR)
• Instruction cache data port register (read-only) (IC_DAT)
These registers are privileged and any attempt to access them while the core is in the
problem state (MSR
PR
=1) results in a program interrupt.
Figure 9-2. Cache Data Path Block Diagram
4
WORDS
LINE
BUFFER
INSTRUCTION
INTERNAL BUS DATA
16K
SET
ADDRESS [20:27]
4
ADDRESS [28:29]
CACHE
ARRAY
DECODER
128
32
WORDS
BURST
BUFFER
128
128
128
STREAM
HIT
MUX
2->1
WORD
SELECT
MUX
4->1
128
DATA
BYPASS
MUX
2->1
32
32
TO CORE