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Motorola MPC823e User Manual
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Instruction Execution Timing
MOTOROLA
MPC823e REFERENCE MANUAL
8-7
INSTRUCTION EXECUTION
8
TIMING
8.2.3 Fastest External Load (Data Cache Miss)
lwz
r12,64 (SP)
sub
r3,r12,3
addic
r4,r14,1
The
sub
instruction is dependent on the value read by the load. It causes three bubbles in
the instruction execution stream. The external clock is shifted 90
°
relative to the internal
clock.
Figure 8-5. Example of an External Load
SUB
LWZ
LWZ
SUB
ADDIC
SUB
SUB
LWZ
BUBBLE
LWZ
LWZ
LWZ
LWZ
LWZ
LWZ
GCLK1
E DATA
FETCH
DECODE
READ + EXECUTE
WRITEBACK
L ADDRESS DRIVE
L DATA
CACHE ADDRESS
LOAD WRITEBACK
E ADDRESS
BUBBLE
BUBBLE
BUBBLE
185
187
Table of Contents
Table of Contents
3
List of Tables
44
Features
49
Section 1 Introduction
49
Architecture
54
The Embedded Powerpc Core
56
The System Interface Unit
56
The Communication Processor Module
57
The Video/Lcd Controller
58
The Video Controller
58
The LCD Controller
58
The PCMCIA-ATA Controller
58
Power Management
59
System Debug Support
59
Applications
59
Differences between MPC823 (Rev B) and Mpc823E
60
Mpc823E Glueless System Design
60
External Signals
62
The System Bus Signals
63
Memory Map
77
Reset
89
Types of Reset
90
Power-On Reset
90
External Hard Reset
91
Internal Hard Reset
91
Loss of Lock
91
Software Watchdog Reset
91
Checkstop Reset
91
Debug Port Hard Reset
91
JTAG Reset
91
External Soft Reset
92
Internal Soft Reset
92
Debug Port Soft Reset
92
Reset Status Register
93
How to Configure Reset
95
Hard Reset
95
Hard Reset Configuration Word
98
Soft Reset
100
Clocks and Power Control
101
Features
101
Register Model
103
System Clock and Reset Control Register
103
PLL, Low-Power, and Reset Control Register
107
The Clock Module
110
On-Chip Oscillators and External Clock Input
112
System PLL
112
SPLL Stability
113
The Low-Power Clock Divider
114
Internal Clock Signals
116
The General System Clocks
116
The Baud Rate Generator Clock
120
The Synchronization Clocks
120
The LCD Clocks
121
Clock Configuration
122
Mode Clock Pins
122
The System Phase-Locked Loop Pins
123
Power Control
124
Power Rails
124
Keep-Alive Power
125
Power Switching Example
126
Low-Power Operation
128
The Powerpc Core
132
Features
132
Basic Structure of the Core
133
Instruction Flow Within the Core
133
Basic Instruction Pipeline
135
Sequencer Unit
135
Flow Control
136
Issuing Instructions
137
Interrupts
138
Implementing the Precise Exception Model
139
Restartability after an Interrupt
141
Processing an Interrupt
142
Serialization
143
Latency
143
The External Interrupt
144
Latency
144
Interrupt Ordering
145
The Register Unit
146
Control Registers
147
Physical Location of Special Registers
150
Powerpc Standard Control Register Bit Assignment
151
Machine State Register
151
The Condition Register
153
Fixed-Point Exception Cause Register
154
Initializing the Control Registers
155
System Reset Interrupt
155
Hard/Soft Reset
155
The Fixed-Point Unit
155
XER Update in Divide Instructions
155
The Load/Store Unit
156
Issuing Load/Store Instructions
157
Serializing Load/Store Instructions
158
Instructions Issued to the Data Cache
158
Issuing Store Instruction Cycles
158
Issuing Nonspeculative Load Instructions
158
Executing Unaligned Instructions
159
Little-Endian Mode Support
160
Atomic Update Primitives
160
Instruction Timing
161
Stalling Storage Control Instructions
161
Accessing Off-Core Special Registers
161
Storage Control Instructions
162
Exceptions
162
DAR, DSISR, and BAR Operation
162
Powerpc Architecture Compliance
163
Powerpc User Instruction Set Architecture (Book I)
163
Computation Modes
163
Reserved Fields
163
Classes of Instructions
163
Exceptions
164
The Branch Processor
164
Fetching Instructions
164
Branch Instructions
164
Invalid Branch Instruction Forms
164
Branch Prediction
164
The Fixed-Point Processor
164
Move To/From System Register Instructions
164
Fixed-Point Arithmetic Instructions
165
The Load/Store Processor
165
Fixed-Point Load with Update and Store
165
Fixed-Point Load and Store Multiple Instructions
165
Fixed-Point Load String Instructions
165
Storage Synchronization Instructions
166
Optional Instructions
166
Little-Endian Byte Ordering
166
Powerpc Virtual Environment Architecture (Book II)
166
Storage Model
166
Memory Coherence
166
Atomic Update Primitives
166
The Effect of Operand Placement on Performance
167
The Storage Control Instructions
167
Timebase
168
Powerpc Operating Environment Architecture (Book III)
168
The Branch Processor
168
Machine State Register
168
Processor Version Register
168
Branch Processors Instructions
168
The Fixed-Point Processor
168
Unsupported Registers
168
Added Registers
168
Storage Model
168
Reference and Change Bits
169
Storage Protection
169
Storage Control Instructions
169
Data Cache Block Invalidate (Dcbi)
169
TLB Invalidate Entry (Tlbie)
169
TLB Invalidate All (Tlbia)
169
TLB Synchronize (Tlbsync)
169
Interrupts
169
Classes
169
Processing
170
Definitions
170
System Reset Interrupt
171
Machine Check Interrupt
171
Data Storage Interrupt
172
Instruction Storage Interrupt
172
Alignment Interrupt
172
Program Interrupt
173
Trace Interrupt
173
Implementation-Dependent Software Emulation Interrupt
174
Implementation-Specific Instruction TLB Miss Interrupt
174
Implementation-Specific Instruction TLB Error Interrupt
175
Implementation-Specific Data TLB Miss Interrupt
176
Implementation-Specific Data TLB Error Interrupt
176
Implementation-Specific Debug Register
177
Partially Executed Instructions
179
Timer Facilities
179
Optional Facilities and Instructions
179
Instruction Execution Timing
180
Instruction Timing List
180
Instruction Execution Timing Examples
183
Data Cache Load
183
Writeback
184
Writeback Arbitration
184
Private Writeback Bus Load
185
Fastest External Load (Data Cache Miss)
186
A Full History Buffer
187
Branch Folding
188
Branch Prediction
189
Instruction Cache
190
Features
190
Programming the Instruction Cache
193
Instruction Cache Control and Status Register
194
Instruction Cache Address Register
195
Instruction Cache Data Port Register
196
Instruction Cache Operation
196
Instruction Cache Hit
196
Instruction Cache Miss
197
Instruction Fetch on a Predicted Path
197
Instruction Cache Commands
197
Invalidating the Instruction Cache
198
Loading and Locking the Instruction Cache
199
Unlocking a Line
199
Unlocking the Entire Instruction Cache
200
Inhibiting the Instruction Cache
200
Instruction Cache Read
201
Instruction Cache Write
203
Restrictions
203
Instruction Cache Coherency
203
Updating Code and Memory Region Attributes
203
Reset Sequence
203
Debug Support
204
Fetching Instructions from the Development Port
204
Data Cache
205
Features
205
Organization of the Data Cache
206
Programming the Data Cache
207
Powerpc Architecture Instructions
207
Powerpc User Instruction Set Architecture (Book I)
207
Powerpc Virtual Environment Architecture (Book II)
208
Powerpc Operating Environment Architecture (Book III)
208
Implementation-Specific Operations
208
Special Registers of the Data Cache
208
Data Cache Control and Status Register
208
Data Cache Address Register
208
Reading the Cache Structures
211
Operating the Data Cache
214
Data Cache Read
214
Data Cache Write
214
Copyback Mode
215
Writethrough Mode
216
Data Cache Inhibited Accesses
216
Data Cache Freeze
216
Data Cache Coherency
217
Data Cache Commands
217
Flushing and Invalidating the Cache
217
Enabling and Disabling the Cache
217
Locking and Unlocking the Cache
217
Data Cache Instructions
218
Dcbi, Dcbst, Dcbf and Dcbz Instructions
218
Touch
218
Storage Synchronization/Reservation
218
Data Cache Read
218
Memory Management Unit
219
Features
219
Address Translation
220
Translation Lookaside Buffer Operation
220
Protection
221
Storage Control
222
Translation Table Structure
223
Level One Descriptor
227
Level Two Descriptor
228
Programming the Memory Management Unit
233
Control Registers
234
MMU Instruction Control Register
234
MMU Data Control Register
235
MMU Current Address Space ID Register
236
MMU Instruction Effective Page Number Register
237
MMU Data Effective Page Number Register
238
MMU Instruction Real Page Number Register
239
MMU Data Real Page Number Register
244
MMU Instruction Access Protection Register
249
MMU Data Access Protection Register
250
MMU Instruction Tablewalk Control Register
251
MMU Data Tablewalk Control Register
252
MMU Tablewalk Base Register
254
MMU Tablewalk Special Register
255
MMU Data Content-Addressable Registers
255
MMU Data CAM Entry Read Register
256
MMU Data RAM Entry Read Register 0
257
MMU Data RAM Entry Read Register 1
259
MMU Instruction Content-Addressable Registers
261
MMU Instruction CAM Entry Read Register
261
MMU Instruction RAM Entry Read Register 0
263
MMU Instruction RAM Entry Read Register 1
264
Interrupts
265
Implementation-Specific Instruction TLB Miss
265
Implementation-Specific Data TLB Miss
265
Implementation-Specific Instruction TLB Error
266
Implementation-Specific Data TLB Error
266
Manipulating the Translation Lookaside Buffer
267
Reloading the Translation Lookaside Buffer
267
Translation Reload Examples
268
Controlling the TLB Replacement Counter
269
Invalidating the Translation Lookaside Buffer
269
Loading the Reserved TLB Entries
269
Requirements for Accessing the Memory Management Unit Control Registers
270
System Interface Unit
271
Features
272
System Configuration and Protection
272
Interrupt Configuration
275
The Interrupt Structure
275
Priority of the Interrupt Sources
276
Programming the Interrupt Controller
277
SIU Interrupt Pending Register
277
SIU Interrupt Mask Register
278
SIU Interrupt Edge/Level Register
279
SIU Interrupt Vector Register
280
The Bus Monitor
281
The Powerpc Decrementer
282
Decrementer Register
283
The Powerpc Timebase
284
Timebase Register
284
Timebase Reference Registers
285
Timebase Status and Control Register
286
The Real-Time Clock
287
Real-Time Clock Status and Control Register
288
Real-Time Clock Register
289
Real-Time Clock Alarm Seconds Register
290
Real-Time Clock Alarm Register
291
The Periodic Interrupt Timer
292
Periodic Interrupt Status and Control Register
293
Periodic Interrupt Timer Count Register
294
Periodic Interrupt Timer Register
295
The Software Watchdog Timer
296
Software Service Register
297
Freeze Operation
298
Low-Power Stop Operation
298
Multiplexing the System Interface Unit Pins
299
Programming the System Interface Unit
300
System Configuration and Protection Registers
300
SIU Module Configuration Register
300
Internal Memory Map Register
304
System Protection Control Register
305
Transfer Error Status Register
306
External Bus Interface
308
Features
308
Transfer Signals
308
Control Signals
310
Bus Signal Descriptions
311
Bus Interface Operation
314
Basic Transfers
315
Single Beat Transfers
315
Single Beat Read Flow
316
Single Beat Write Flow
319
Burst Transfers
323
The Burst Mechanism
323
Transfer Alignment and Packaging
332
Arbitration Phase-Related Signals
334
Bus Request Signal
335
Bus Grant Signal
336
Bus Busy Signal
336
Address Transfer Phase-Related Signals
338
Transfer Start Signal
338
Address Bus
339
Transfer Attributes
339
Read/Write Signal
339
Burst Signal
339
Transfer Size Signal
340
Address Space Attributes
340
Special Transfer Start Signal
340
Burst Data in Progress Signal
343
Data Transfer Phase-Related Signals
343
Data Signal
343
Termination Phase-Related Signals
343
Transfer Acknowledge Signal
343
Burst Inhibit Signal
343
Transfer Error Acknowledge Signal
343
Protocol for Termination Signals
344
Storage Reservation Protocol
345
Exception Control Cycles
348
RETRY Signal
349
Endian Modes
354
Little-Endian Features
356
Big-Endian System Features
358
Powerpc Little-Endian System Features
358
Setting the Endian Mode of Operation
358
Memory Controller
359
Features
359
Architecture
362
Register Model
365
Register Descriptions
367
Base Registers
367
The Ram Array
406
Uart Baud Rate Examples
616
Handling Interrupts in the Spi
909
The Port B Registers
939
Port D Registers
951
Pcmcia Controller Timing Examples
988
Lcd Controller Operation
1005
Basic Operation
1077
Debug Mode Registers
1116
The Tap Controller
1124
Ordering Information
1147
4
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Motorola MPC823e Specifications
General
Brand
Motorola
Model
MPC823e
Category
Computer Hardware
Language
English
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