Motorola MPC823e

PowerPC Architecture Compliance
7-14 MPC823e REFERENCE MANUAL MOTOROLA
PPC ARCHITECTURE
7
COMPLIANCE
MSR—Machine State Register
IP No change.
ME No change.
LE Bits are copied from the ILE.
Other Set to 0.
Some instruction TLB registers are set to a value described in
Section 11 Memory Management Unit. Execution resumes at offset x’01300’ from the
base address indicated by MSR
IP
.
7.3.7.3.13 Implementation-Specific Data TLB Miss Interrupt. This type of interrupt
occurs when MSR
DR
=1 and you try to access a page whose effective page number cannot
be translated by TLB. The following registers are set:
SRR0—Save/Restore Register 0
Set to the effective address of the instruction that caused the interrupt.
SRR1—Save/Restore Register 1
1–4 Set to 0.
10–15 Set to 0.
Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
RI
.
MSR—Machine State Register
IP No change.
ME No change.
LE Bits are copied from the ILE.
Other Set to 0.
Some instruction TLB registers are set to the values described in
Section 11 Memory Management Unit. Execution resumes at offset x’01200’ from the
base address indicated by MSR
IP
.
7.3.7.3.14 Implementation-Specific Data TLB Error Interrupt. This type of interrupt
occurs as a result of one of the following conditions:
• No effective address of a load, store, icbi, dcbz, dcbst, dcbf or dcbi instruction can
be translated (either the segment or page valid bit of this page is cleared in the
translation table).
• The access violates storage protection.
• An attempt was made to write to a page with a negated change bit.
The following registers are set:
SRR0—Save/Restore Register 0
Set to the effective address of the instruction that caused the interrupt.