External Bus Interface
MOTOROLA MPC823e REFERENCE MANUAL 13-27
EXTERNAL BUS
13
INTERFACE
Table 13-3 lists the patterns of the data transfer for write cycles when accesses are initiated
by the MPC823e.
13.4.6 Arbitration Phase-Related Signals
The external bus design provides for a single bus master, either the MPC823e or an external
device. One or more of the external devices on the bus has the capability of becoming bus
master for the external bus. Bus arbitration may be handled either by an external central bus
arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for one
external bus master besides the MPC823e. The arbitration configuration (external or
internal) is set at system reset. See Section 15.6 External Master Support for more
information.
Each bus master must have BR
, BG, and BB signals. The device that needs the bus asserts
the BR
signal. The device then waits for the arbiter to assert the BG signal. In addition, the
new master must look at the BB
signal to ensure that no other master is driving the bus
before it can assert BB
and assume ownership of the bus. If the arbiter has taken the BG
away from the master and the master wants to execute a new cycle, the master must
rearbitrate before a new cycle can be initiated. The MPC823e, however, guarantees data
coherency for burst accesses to a small port size. This means that the MPC823e will not
release the bus until the transactions (atomic) complete.
Table 13-3. Data Bus Contents for Write Cycles
TRANSFER
SIZE
TSIZE
[0:1]
INTERNAL
ADDRESS
EXTERNAL DATA BUS PATTERN
A30 A31 D0–D7 D8–D15 D16–D23 D24–D31
Byte 0100 OP0 — — —
0101 OP1 OP1 — —
0110 OP2 — OP2 —
0111 OP3 OP3 — OP3
Half-Word 1000 OP0 OP1 — —
1010 OP2 OP3 OP2 OP3
Word 0000 OP0 OP1 OP2 OP3
NOTE: — Denotes that a byte is not required during that write cycle.
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