Motorola MPC823e User Manual

Memory Management Unit
MOTOROLA MPC823e REFERENCE MANUAL 11-17
MEMORY MANAGEMENT
11
UNIT
ITLB_INDX—Instruction TLB Index
This field acts as a pointer to the instruction TLB entry to be loaded. It is automatically
decremented at every instruction translation lookaside buffer update.
Bits 24–31—Reserved
These bits are reserved and must be set to 0. Ignored on write and returns a 0 on read.
11.6.1.2 MMU DATA CONTROL REGISTER. The MMU data control register (MD_CTR) is
a special register that is used to control the operation of the data memory management
unit.GPM—Group Protection Mode
0 = PowerPC mode.
1 = Domain manager mode.
PPM—Page Protection Mode
0 = Page resolution protection.
1 = 1K resolution protection for a 4K page.
CIDEF—CI Default
This bit is the data cache attributes default value when the data MMU is disabled
(MSR
DR
= 0).
WTDEF—WT Default
This bit is the data cache attributes default value when the data MMU is disabled
(MSR
DR
= 0).
RSV4D—Reserve Four Data TLB Entries
0 = DTLB_INDX decremented modulo 32.
1 = DTLB_INDX decremented modulo 28.
MD_CTR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
GPM PPM CIDEF WTDEF RSV2D TWAM PPCS RESERVED
RESET
0000000 0
R/W
R/W R/WR R/W R/W R/W R/W R/W R/W
ADDR
SPR 792
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
RESERVED DTLB_INDX RESERVED
RESET
00 0
R/W
R/W R/W R/W
ADDR
SPR 792

Motorola MPC823e Specifications

General

Brand	Motorola
Model	MPC823e
Category	Computer Hardware
Language	English