System Interface Unit
12-30 MPC823e REFERENCE MANUAL MOTOROLA
SYSTEM INTERFACE UNIT
12
12.12 PROGRAMMING THE SYSTEM INTERFACE UNIT
12.12.1 System Configuration and Protection Registers
12.12.1.1 SIU MODULE CONFIGURATION REGISTER. The SIU module configuration
register (SIUMCR) contains bits that configure various features in the system interface unit.
EARB—External Arbitration
If the EARB bit is set, then external arbitration is assumed. If it is cleared, internal arbitration
is performed. For more information, see Section 13.4.6 Arbitration Phase-Related
Signals.
EARP—External Arbitration Request Priority
This field defines the priority of the external master’s arbitration request. This field is valid
when EARB is cleared. 000 is the lowest priority level and 111 the highest. For more
information, refer to Figure 13-20 in Section 13 External Bus Interface.
Bits 4–7, 13, 24, and 28–31—Reserved
These bits are reserved and must be set to 0.
DSHW—Data Show Cycles
This bit selects the show cycle mode to be applied to data cycles. Instruction show cycles
are programmed in the ICTRL register. Refer to Section 20.6.2 Development Port
Registers for more information. This bit is locked by the DLK bit.
0 = Disable show cycles for all internal data cycles.
1 = Show address and data of all internal data cycles.
SIUMCR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
EARB EARP RESERVED DSHW DBGC DBPC RES FRC DLK
RESET
00 0 000000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x000
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
OPAR PNCS DPC MPRE MLRC AEME SEME RES GB5E B2DD B3DD RESERVED
RESET
0000 0 000000 0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000)
+
0x002
To Next Page
Loading...
