Instruction Cache
MOTOROLA
MPC823e REFERENCE MANUAL
9-5
INSTRUCTION CACHE
9
9.2.1 Instruction Cache Control and Status Register
The instruction cache control and status register (IC_CST) is used to configure and access
the status of the instruction cache.
IEN—Instruction Cache Enable Status
This read-only bit indicates the status of the instruction cache. Any attempt to write to it is
ignored. You can enable or disable the instruction cache by writing to the CMD field.
0 = Instruction cache is disabled.
1 = Instruction cache is enabled.
Bits 1–3—Reserved
These bits are reserved and must be set to 0.
CMD—Command
The following commands can be written to the CMD field to control and configure the
instruction cache. The machine must be in privilege mode (MSR
PA
=1).
000 = Reserved.
001 =
CACHE ENABLE
.
010 =
CACHE DISABLE
.
011 =
LOAD & LOCK
.
100 =
UNLOCK LINE
.
101 =
UNLOCK ALL
.
110 =
INVALIDATE ALL
.
111 = Reserved.
Bits 7–9—Reserved
These bits are reserved and must be set to 0.
IC_CST
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
IEN RESERVED CMD RESERVED CCER1 CCER2 CCER3 RESERVED
RESET
00000000
R/W
R — R/W — R R R —
SPR
560
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
RESERVED
RESET
0
R/W
—
SPR
560
NOTE: — = Undefined.