Motorola MPC823e - MMU Data Tablewalk Control Register

Memory Management Unit
11-34 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY MANAGEMENT
11
UNIT
V—Entry Valid
Default value on instruction TLB miss is 1.
0 = Entry is not valid.
1 = Entry is valid.
11.6.1.11 MMU DATA TABLEWALK CONTROL REGISTER. The MMU data tablewalk
control (MD_TWC) register contains the second level pointer and access protection group
of an entry to be loaded into the translation lookaside buffer.
L2TB—Tablewalk Level 2 Base Value
These bits are the most-significant bits of the level two pointer.
Bits 20–22—Reserved
When written, these bits are reserved and must be set to 0. When read, they return
MD_EPN[10:19] when MD_CTR
TWAM
= 1 and MD_EPN[12:21] when MD_CTR
TWAM
= 0.
APG—Access Protection Group
When written, this field supports a maximum of 16 protection groups. It is set to 0000 on the
data TLB miss. When read, it returns MD_EPN[10:19] when MD_CTR
TWAM
= 1 and
MD_EPN[12:21] when MD_CTR
TWAM
= 0.
G—Guarded
When written, this bit of the entry has the following settings and is set to 0 on a data TLB
miss:
0 = Unguarded storage.
1 = Guarded storage.
MD_TWC
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD L2TB
RESET —
R/W R/W
ADDR SPR 797
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD L2TB RESERVED APG G PS WT V
RESET ———————
R/W R/W R/W R/W R/W R/W R/W R/W
ADDR SPR 797
NOTE: — = Undefined.