Memory Management Unit
MOTOROLA MPC823e REFERENCE MANUAL 11-31
MEMORY MANAGEMENT
11
UNIT
11.6.1.8 MMU INSTRUCTION ACCESS PROTECTION REGISTER. The MMU instruction
access protection (MI_AP) register contains the access protection group for the instruction
memory management unit.
GPx—Group Protection
In domain manager mode, these bits have the following settings.
00 = No access.
01 = Client-access permission defined by page protection bits.
10 = Reserved.
11 = Manager-free access.
In PowerPC mode, the GPx bits have these settings and are privilege and problem state
(Ks and Kp) in the
PowerPC Microprocessor Family: The Programming Environment for
32-Bit Microprocessors
manual:
00 = All accesses are considered privileged.
01 = Access permission defined by page protection bits.
10 = Problem and privileged interpretation is swapped.
11 = All accesses are considered problem.
MI_AP
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7
RESET ————————
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR SPR 786
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD GP8 GP9 GP10 GP11 GP12 GP13 GP14 GP15
RESET ————————
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR SPR 786
NOTE: — = Undefined.
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