Motorola MPC823e - MMU Data Effective Page Number Register

Memory Management Unit
11-20 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY MANAGEMENT
11
UNIT
11.6.1.5 MMU DATA EFFECTIVE PAGE NUMBER REGISTER. The MMU data effective
page number (MD_EPN) register contains the effective address to be loaded into a TLB
entry.
EPN—Effective Page Number for Entry
The default value is the effective address of the last data TLB miss.
EV—TLB Entry Valid
This bit is set to 1 on a data TLB miss.
0 = The data TLB entry is invalid.
1 = The data TLB entry is valid.
Bits 20-21 and 23–27—Reserved
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read.
ASID—Address Space ID
This field is the address space IDs of the TLB entry to be compared with the CASID field of
the M_CASID register.
MD_EPN
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD EPN
RESET —
R/W R/W
ADDR SPR 795
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD EPN RES EV RESERVED ASID
RESET ——— 0 —
R/W R/W R/W R/W R/W R/W
ADDR SPR 795
NOTE: — = Undefined.