Motorola MPC823e

Data Cache
10-4 MPC823e REFERENCE MANUAL MOTOROLA
DATA CACHE
10
10.3.1.2 P
OWER
PC VIRTUAL ENVIRONMENT ARCHITECTURE (BOOK II)
The data cache supports the following instructions:
• Data cache block flush ( dcbf )
• Data cache block store ( dcbst )
• Data cache block touch ( dcbt )
• Data cache block touch for store ( dcbtst )
• Data cache block set to zero ( dcbz )
10.3.1.3 P
OWER
PC OPERATING ENVIRONMENT ARCHITECTURE (BOOK III). The
data cache supports the dcbi (data cache block invalidate) instruction.
10.3.2 Implementation-Specific Operations
The MPC823e data cache includes some extended features in addition to those of the
PowerPC architecture. The following are implementation-specific operations supported by
the MPC823e:
• Block lock
• Block unlock
• Invalidate all
• Unlock all
• Flush cache line
• Read tags
• Read registers
10.3.3 Special Registers of the Data Cache
The PowerPC special registers are accessed via the mtspr and mfspr instructions. The
following registers are used to control the data cache:
• Data cache control and status register (DC_CST)
• Data cache address register (DC_ADR)
• Data cache data register (DC_DAT)
These registers are privileged and any attempt to access them while the core is in the
problem state (MSR
PR
=1) results in a program interrupt.