Motorola MPC823e User Manual

Clocks and Power Control
MOTOROLA MPC823e REFERENCE MANUAL 5-3
CLOCKS AND POWER
5
CONTROL
5.2 REGISTER MODEL
5.2.1 System Clock and Reset Control Register
The SPLL has a 32-bit control register that is powered by keep-alive power. The system
clock and reset control register (SCCR) is memory-mapped into the MPC823e system
interface unit’s register map.
Bits 0 and 3–5—Reserved
These bits are reserved and must be set to 0.
COM—Clock Output Module
This field controls the output buffer strength of the CLKOUT pin. When both bits are set, the
CLKOUT pin is held in the high state. These bits can be dynamically changed without
generating spikes on the CLKOUT pin. If the CLKOUT pin is not connected to external
circuits, both bits are must be set to minimize noise and power dissipation. The COM field
is cleared by hard reset.
00 = Clock output enabled full-strength buffer.
01 = Clock output enabled half-strength output buffer.
10 = Reserved.
11 = Clock output disabled.
SCCR
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
RES COM RESERVED TBS RTDIV RTSEL CRQEN PRQEN RESERVED EBDF RES
HRESET
— # 0 ###00 0
†
0
POR
00 0 0
**
00 0
†
0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x280
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
RES DFSYNC DFBRG DFNL DFNH DFLCD DFALCD
HRESET
0000000
POR
0000000
R/W
R/W R/W R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x282
NOTE: HRESET is hard reset and POR is power-on reset.
—
= undefined and # = unaffected.
* RTDIV depends on the combination of MODCK1and MODCK2. RTSEL depends on MODCK1.
See Table 5-2 for more information.
† This field is set according to the default of the hard reset configuration word.

Motorola MPC823e Specifications

General

Brand	Motorola
Model	MPC823e
Category	Computer Hardware
Language	English