Motorola MPC823e

Clocks and Power Control
5-16 MPC823e REFERENCE MANUAL MOTOROLA
CLOCKS AND POWER
5
CONTROL
5.3.4 Internal Clock Signals
The internal logic of the MPC823e uses the following internal clock signals:
• General system clocks
• Baud rate generator clock
• Synchronization clocks
• LCD clocks
The MPC823e also generates an external clock signal called CLKOUT. All internal clock
signals originate from the same source, so they are all synchronized to VCOOUT.
5.3.4.1 THE GENERAL SYSTEM CLOCKS. The general system clocks—GCLK1C,
GCLK2C, GCLK1, GCLK2, GCLK1_50, and GCLK2_50—are the basic clocks supplied to
all modules of the MPC823e. GCLKxC is supplied to the core, data and instruction caches,
and memory management unit. It is not active when the core is in sleep or power-down
mode. GCLKx is supplied to the system interface unit, clock module, memory controller, and
most of the other blocks in the communication processor module.
The timing relationship between the general system clock signals that are shown in
Figure 5-1 is illustrated in Figure 5-6. CLKOUT, the only externally visible clock, is derived
from the GCLK2_50 signal.
Figure 5-6. MPC823e Clocks Timing Diagram
GCLK1
GCLK2
GCLK1_50
GCLK2_50
CLKOUT
GCLK1_50
GCLK2_50
(EBDF=00)
(EBDF=00)
(EBDF=01)
(EBDF=01)
CLKOUT
(EBDF=00)
(EBDF=01)