Introduction
1-12
MPC823e REFERENCE MANUAL
MOTOROLA
INTRODUCTION
1
1.7 DIFFERENCES BETWEEN MPC823 (REV 1) AND MPC823e
The following modifications were made to the MPC823 Revision 1 to create the MPC823e:
• Core operation was increased to 99MIPS @ 75MHz or 172K Dhyrstones
• The instruction cache was increased to 16K
• There are twenty serial DMA channels for reception and transmission
• The data cache was increased to 8K
• The instruction and data memory management units each consist of 32 TLB entries
• A time-division multiplex channel (TDMB) was added to the serial interface
1.8 MPC823e GLUELESS SYSTEM DESIGN
The MPC823e was primarily designed to make it easy for you to interface a microprocessor
with other system components. Figure 1-2 illustrates a system configuration that contains
one flash EPROM and yet supports DRAM SIMM and one SRAM. Although the MPC823e
supports a glueless interface to DRAM, the capacitance of the system bus may require that
there be external buffers. From a logic standpoint, however, a glueless system is
maintained.
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