LCD Controller
MOTOROLA MPC823e REFERENCE MANUAL 18-25
LCD CONTROLLER
18
18.4.3 LCD Vertical Configuration Register
The 32-bit, memory-mapped, read/write LCD vertical control register (LCVCR) holds the
panel vertical pixel resolution and other configuration parameters.
VPW—Vertical Sync Pulse Width (with active (TFT) panels only)
This field controls the width of the active FRAME/VSYNC signal with its value represented
in line units. Programming this field to
n
causes FRAME/VSYNC to be active for
n
lines. This
field is only valid for TFT displays and must be cleared for all others.
Bits 4–6 and 21—Reserved
These bits are reserved and must be set to 0.
LCD_AC—LCD AC Timing
This field specifies the number of frames that are displayed before the LCD_AC/LOE pin is
toggled.
LCVCR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD VPW RESERVED LCD_AC VPC
RESET 000 0
R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x
848
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD VPC RES WBF
RESET 00 0
R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x
84A
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