Video Controller
MOTOROLA
MPC823e REFERENCE MANUAL
19-3
VIDEO CONTROLLER
19
19.2.1 The Video Controller Clock
The video controller master clock source can either be the LCDCLK, which is generated by
the system interface unit, or the external video clock signal (CLK). Refer to
Section 5.2.1 System Clock and Reset Control Register
and
Section 5.3.4.4 The LCD
Clocks
for more information. LCDCLK is derived from the SPLL. If the external video clock
is enabled by setting the CSRC bit in the VCCR, you must provide an external video clock
(CLK) at the port D input.
Figure 19-2. Video Controller Block Diagram
Note:
If an external video clock (CLK) is used, then the ratio between that external
clock and GCLK1 must not be greater than 1.25:1. For example, if your system
clock is 50MHz, then the CLK input cannot exceed 62.5MHz.
FIFO
HSYNC
8-BIT DATA
FIFO
MUX
CONFIGURATION
REGISTERS
VSYNC
FIELD
BLANK
ACTIVE PIXELS
BACKGROUND
DMA
DMA INTERFACE
CONTROLLER
PIXELS
U-BUS
VIDEO
CONTROL
RAM
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