Motorola MPC823e - Page 1040

Video Controller
19-6 MPC823e REFERENCE MANUAL MOTOROLA
VIDEO CONTROLLER
19
DPF—Default Pixels Format
This bit defines the format of the background video components.
0 = BGND1, BGND2, BGND3 values will be used for the inactive area (BGND1,
BGND2, BGND3, BGND1, BGND2, BGND3,....). This setting is used for RGB
encoding.
1 = BGND1, BGND2, BGND3, BGND4 values will be used for the inactive area
(BGND1, BGND2, BGND3, BGND4, BGND1, BGND2, BGND3, BGND4,...). This
setting is used for YC
r
C
b
format encoding (Y
1
C
r
Y
2
C
b
).
Bits 3 and 13—Reserved
These bits are reserved and must be set to 0.
IEN—Interrupt Enable
0 = The end-of-frame (EOF) interrupt is disabled.
1 = The end-of-frame (EOF) interrupt is enabled.
EIEN—Exception Interrupt Enable
0 = The underrun/bus error interrupt is disabled.
1 = The underrun/bus error interrupt is enabled.
IRQL—Interrupt Request Level
This field contains the priority request level of the video controller’s interrupt that is sent to
the system interface unit. Refer to Section 12.3.3 Programming the Interrupt Controller
for more information. This will generate an interrupt request level with a vector in the SIVEC
register if enabled with the SIMASK register. Both EOF and the exception interrupts use the
same request level. 000 is the highest priority level and 111 is the lowest.
BO—Byte Order
0 = PowerPC little-endian byte order.
1 = Big- or little-endian byte order.
AT—Address Type
This field contains the value that you want to appear on the AT pins when the associated
SDMA channel accesses memory. AT0 will always be driven to 1. Refer to
Section 13.4.7.3.4 Address Space Attributes for address type descriptions.
CSRC—Clock Source
This bit controls the clock source to the video controller.
0 = The video controller source is LCDCLK.
1 = The video controller source is the SHIFT/CLK/CLK pin (PD3).
VON—Video Controller On
0 = Video controller operation is disabled.
1 = Video controller operation is enabled.