Clocks and Power Control
MOTOROLA
MPC823e REFERENCE MANUAL
5-5
CLOCKS AND POWER
5
CONTROL
EBDF—External Bus Division Factor
This field defines the frequency division factor between GCLKx and GCLKx_50. CLKOUT
is similar to GCLK2_50. The GCLKx_50 is used by the bus interface and memory controller
to interface with an external system. This field is initialized during hard reset using the hard
reset configuration word described in
Section 4.3.1.1 Hard Reset Configuration Word
.
00 = CLKOUT is GCLK2 divided by 1.
01 = CLKOUT is GCLK2 divided by 2.
1x = Reserved.
DFSYNC—Division Factor for the SYNCCLK
This field sets the VCOOUT frequency division factor for the SYNCCLK signal. Changing
the value of this field does not result in a loss-of-lock condition. This field is cleared by a
power-on or hard reset.
00 = Divide by 1 (normal operation).
01 = Divide by 4.
10 = Divide by 16.
11 = Divide by 64.
DFBRG—Division Factor of the BRGCLK
This field sets the VCOOUT frequency division factor for the BRGCLK signal. Changing the
value of this field does not result in a loss-of-lock condition. This field is cleared by a
power-on or hard reset.
00 = Divide by 1 (normal operation).
01 = Divide by 4.
10 = Divide by 16.
11 = Divide by 64.
DFNL—Division Factor Low Frequency
This field sets the VCOOUT frequency division factor for general system clocks to be used
in low-power mode. In low-power mode, the MPC823e automatically switches to the DFNL
frequency. To select the DFNL frequency, load this field with the divide value and set the
CSRC bit. A loss-of-lock condition will not occur when you change the value of this field. This
field is cleared by a power-on or hard reset.
000 = Divide by 2.
001 = Divide by 4.
010 = Divide by 8.
011 = Divide by 16.
100 = Divide by 32.
101 = Divide by 64.
110 = Reserved.
111 = Divide by 256.
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