Development Capabilities and Interface
MOTOROLA MPC823e REFERENCE MANUAL 20-21
DEVELOPMENT
20
CAPABILITIES & INTERFACE
You can work in debug mode directly out of reset or the core can be programmed to enter
into the debug mode as a result of a predefined sequence of events. These events can be
any interrupt or exception in the core system (including the internal breakpoints) in addition
to two levels of development port requests and one peripheral breakpoint request generated
internally and externally. Each of these can be programmed as a regular interrupt that
causes the machine to branch to its interrupt vector or as a special interrupt that causes
debug mode entry. When in debug mode, the rfi instruction returns the machine to its
regular work mode. The relationship between debug mode logic and the rest of the core is
illustrated in the following figure.
The development port provides a full-duplex serial interface for communication between the
internal development support logic of the core and an external development tool. The
development port can operate in two working modes—trap enable mode and debug mode.
Figure 20-5. Relationship Between the CPU and Debug Mode
DEVELOPMENT PORT
DEVELOPMENT PORT
ICR
DER
CORE
9
CONTROL LOGIC
SHIFT REGISTER
BKPT, TE,
VSYNC
DPIR
DSCK
DSDI
TECR DPDR
35
32
32
INTERNAL
BUS
DEVELOPMENT
PORT SUPPORT
LOGIC
DSDO
VFLS,
FRZ
EXT
BUS
SIU / EBI
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