Motorola MPC823e - Page 1084

Development Capabilities and Interface
MOTOROLA MPC823e REFERENCE MANUAL 20-23
DEVELOPMENT
20
CAPABILITIES & INTERFACE
Figure 20-6 illustrates the debug mode logic implemented in the core.
Figure 20-6. Debug Mode Logic Implementation
DEBUG ENABLE REGISTER (DER)
INTERRUPT CAUSE REGISTER (ICR)
EVENT (CORE INTERRUPT
SETRESET
ICR_OR
FREEZE
RFI
DECODER
Q
DEBUG MODE ENABLE
INTERNAL DEBUG
5
EVENT VALID
MODE SIGNAL
OR EXCEPTION)