Motorola MPC823e - Page 134

The PowerPC Core
MOTOROLA MPC823e REFERENCE MANUAL 6-3
CORE
6
Figure 6-1. Block Diagram of the Core
Figure 6-2. Instruction Flow Conceptual Diagram
WRITEBACK BUS
SOURCE BUSES
CONTROL BUS
BRANCH
L-ADDR
L-DATA
LDST
FIX
LDST
ADDR
IMUL /
IDIV
ALU /GPR
HISTORY
GPR
(32 X 32)
CONTR
REGS
(2 SLOTS / CLOCK)
(4 SLOTS / CLOCK)
INSTRUCTION
QUEUE
UNIT
NEXT ADDRESS
GENERATION
SEQUENCER
CORE
BFU
INSTRUCTION CACHE / INSTRUCTION MMU INTERFACE DATA CACHE / DATA MMU INTERFACE
DATA
EXECUTION UNITS
HISTORY BUFFER
INSTRUCTION QUEUE
BRANCH
UNIT
ISSUE
RETIRE
FETCH
WRITEBACK