Motorola MPC823e User Manual

Instruction Execution Timing
MOTOROLA MPC823e REFERENCE MANUAL 8-3
INSTRUCTION EXECUTION
8
TIMING
Storage Control Instructions:
isync
Serialize Serialize Branch Yes
Order Storage Access:
eieio
1 1 LDST Next Load or Store
is Synchronized
Relative to All Prior
Load or Store
Cache Control:
icbi
1 1 LDST,
I-Cache
No
NOTES: 1. Refer to Table 6-11 for details.
2. Refer to Section 6.4.1 Control Registers .
3. See Table 6-10 for details.
4.
Where:
5.
6. Blocking the multiply instruction is dependent on the subsequent instruction. For any subsequent
multiply instruction, the blockage is 1 clock and for any subsequent divide it is 2 clocks.
7. Assuming nonspeculative aligned access, on-chip memory, and available bus. For details, refer to
Section 6.6.5 Issuing Nonspeculative Load Instructions , Section 6.6.6 Executing Unaligned
Instructions , and Section 6.6.9 Instruction Timing .
8. Although a store (as well as mtspr for special registers external to the core) issued to the load/store
unit buffer frees the core pipeline, the next load or store will not actually be performed on the bus until
the bus is free.
Table 8-1. Instruction Execution Timing (Continued)
INSTRUCTIONS LATENCY BLOCKAGE EXECUTION
UNIT
SERIALIZING
INSTRUCTION
DivisionLatency
NoOverflow 3
⇒
34 divisorLength –
4
------------------------------------------------------


+
Overflow 2
⇒
------------------------------------------------------------------------------------------------------------------------
=
Overflow
x
0
---


or
MaxNegativeNumber
1
–
---------------------------------------------------------------


=
DivisionBlockage DivisionLatency=

Motorola MPC823e Specifications

General

Brand	Motorola
Model	MPC823e
Category	Computer Hardware
Language	English