Instruction Cache
9-2
MPC823e REFERENCE MANUAL
MOTOROLA
INSTRUCTION CACHE
9
• Supports Cache Inhibit
❏
As a cache mode of operation (cache disable)
❏
On memory regions (supported by the memory management unit)
• Efficiently Uses the Pipeline of the Internal Bus by Initiating a New Burst Cycle (if a Miss
is Detected) while Bringing the Tail of the Previously Missed Line to the Cache.
• Performance Enhanced for Cache-Inhibited Regions by Fetching a Full Line to the
Internal Burst Buffer. Instructions Stored in the Burst Buffer and Those Originated in a
Cache-Inhibited Region are Only Used Once before Being Refetched.
• Instruction Unit Request has Priority Over a Burst Buffer Write to an Array (Burst Buffer
Holds Last Missed Data), thus Increasing the Overall Core Performance
• Miss Latency is Reduced by Sending Addresses to the Cache and Internal Bus
Simultaneously and Aborting when a Hit before a Cycle Goes External
• Minimum Operational Power Consumption
• Tags and Data Arrays can be Accessed by the Core for Debugging and Testing
Purposes
• Special Support is Available when the MPC823e Processor is in Debug Mode. Refer to
Section 9.9 Debug Support
for More Information.
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