Memory Management Unit
11-14 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY MANAGEMENT
11
UNIT
LPS—Large Page Size
This bit must be set to 0 for 1K resolution protection.
0 = 1K or 4K.
1 = 16K.
SH—Shared Page
0 = This entry matches only if the ASID field in the TLB entry matches the value of the
M_CASID register.
1 = ASID comparison is disabled for the entry.
CI—Cache Inhibit
This bit is the cache-inhibit attribute for the entry. Setting this bit will inhibit cache fill for
accesses to this page.
V—Valid
This is the page valid bit. Setting this bit indicates the page is valid or resident in the memory
(for demand page memory management).
PAGES OVER 4K WITH 4K RESOLUTION PROTECTION
PP4 SETTING CASE: Mx_CTR (PPCS) = 1
00 Must be zero
01 Reserved
10 Reserved
11 Reserved
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