Memory Management Unit
MOTOROLA MPC823e REFERENCE MANUAL 11-25
MEMORY MANAGEMENT
11
UNIT
LPS—Large Page Size
This bit must be set to 0 for 1K resolution protection.
0 = 1K or 4K.
1 = 16K.
SH—Shared Page
0 = This entry matches only if the ASID filed in the TLB entry matches the value of the
M_CASID register.
1 = ASID comparison is disabled for the entry.
CI—Cache Inhibit
This bit is the cache-inhibit attribute for the TLB entry.
V—Valid
This bit indicates that a TLB entry is valid.
PAGES OVER 4K WITH 4K RESOLUTION PROTECTION
PP4 SETTING CASE: MI_CTR (PPCS) = 1
00 Must be zero
01 Reserved
10 Reserved
11 Reserved
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