Motorola MPC823e - Page 29

TABLE OF CONTENTS (Continued)
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Number Title Number
MOTOROLA MPC823e REFERENCE MANUAL xxvii
19.3.6 Video Frame Buffer A Start Address Register (Set 0) ............19-11
19.3.7 Video Frame Buffer B Start Address Register (Set 0) ............19-12
19.3.8 Video Frame Configuration Register (Set 1) ..........................19-13
19.3.9 Video Frame Buffer A Start Address Register (Set 1) ............19-14
19.3.10 Video Frame Buffer B Start Address Register (Set 1) ............19-15
19.4 Video Controller RAM Array ..............................................................19-16
19.4.1 Video RAM Word Format .......................................................19-17
19.5 Programming Examples ....................................................................19-19
19.5.1 NTSC Example .......................................................................19-20
19.5.1.1 NTSC Programming Procedure Example ...................19-22
19.5.2 PAL Example ..........................................................................19-24
19.5.2.1 PAL Programming Procedure Example ......................19-26
Section 20
Development Capabilities and Interface
20.1 Features ..............................................................................................20-1
20.2 Program Flow Tracking .......................................................................20-2
20.2.1 Basic Operation ........................................................................20-3
20.2.1.1 The Internal Hardware ..................................................20-3
20.2.1.1.1 Special Case Queue Flush Information ...........20-5
20.2.1.1.2 Program Trace In Debug Mode ........................20-5
20.2.1.1.3 Sequential Instructions Marked As Indirect
Branch ...............................................................20-5
20.2.1.2 The External Hardware .................................................20-5
20.2.1.2.1 Back Trace .......................................................20-6
20.2.1.2.2 Window Trace ..................................................20-6
20.2.1.2.3 Synchronizing the Trace Window to the
Internal Core Events .........................................20-6
20.2.1.2.4 Detecting the Trace Window Start Address ......20-7
20.2.1.2.5 Detecting VSYNC Assertion/Negation .............20-7
20.2.1.2.6 Detecting the Trace Window End Address .......20-7
20.2.1.3 Compression of Cancelled Instructions ........................20-8
20.2.2 Controlling Instruction Fetch Show Cycles ...............................20-8
20.3 Generating Watchpoints And Breakpoints ..........................................20-8
20.3.1 Internal Watchpoints and Breakpoints ......................................20-9
20.3.1.1 Restrictions .................................................................20-12
20.3.1.2 Byte And Half-Word Working Modes ..........................20-12
20.3.1.3 Context-Dependent Filter ............................................20-14
20.3.1.4 Ignore First Match Option ...........................................20-15
20.3.1.5 Generating Compare Types .......................................20-15
20.3.2 Basic Operation ......................................................................20-16