Memory Controller
MOTOROLA
MPC823e REFERENCE MANUAL
15-3
MEMORY CONTROLLER
15
Figure 15-1. Memory Controller Block Diagram (Single UPM)
OPTION REGISTER (OR)
BASE REGISTER (BR)
OPTION REGISTER (OR)
BASE REGISTER (BR)
OPTION REGISTER (OR)
BASE REGISTER (BR)
OPTION REGISTER (OR)
OPTION REGISTER (OR)
BASE REGISTER (BR)
OPTION REGISTER (OR)
BASE REGISTER (BR)
OPTION REGISTER (OR)
BASE REGISTER (BR)
OPTION REGISTER (OR)
GENERAL-PURPOSE
CHIP-SELECT
MACHINE
WAIT STATE COUNTER
ATTRIBUTES
SCY[0:3]
USER-
PROGRAMMABLE
MACHINE
MEMORY PERIODIC TIMER
MEMORY COMMAND REGISTER (MCR)
MEMORY DATA REGISTER (MDR)
MEMORY DISABLE TIMER
MACHINE MODE REGISTER (M
x
MR)
TURN ON DISABLE TIMER
ENABLE
UPM ACCESS REQUEST
UPM ACCESS ACKNOWLEDGE
UPM ACCESS REQUEST
UPM COMMAND
BURST, RD/WR
ADDRESS
LATCH
MULTIPLEXER
AND
INCREMENTOR
NA AND
AMX FIELDS
PARITY LOGIC
PARITY ERROR
WP ERROR
DP[0:3]
D[0:31]
(COMMAND)
UPM
ARBITER
DONE
EXPIRED
LOAD
CS
[0:7]
WE
[0:3]
OE
CS[0:7]
BS_
x[0:3]
GPL
x[0:5]
TA
DLT3 (INTERNAL)
UPWAITx
BASE REGISTER (BR)BASE REGISTER (BR)
ADDRESS[0:16], AT[0:2]
(A OR B)
WRITE-PROTECT
LOGIC
WP
RD/WR
MEMORY PERIODIC TIMER PRESCALE REGISTER (MPTPR)
MEMORY STATUS REGISTER (MSTAT)
MEMORY ADDRESS REGISTER (MAR)