Memory Controller
MOTOROLA MPC823e REFERENCE MANUAL 15-19
MEMORY CONTROLLER
15
15.3.1.5 MACHINE A MODE REGISTER. The machine A mode register (MAMR) contains
the configuration for the user-programmable machine A. See Figure 15-1 (page 15-3) for
more information.
PTA—Periodic Timer A Period
This field affects the periodic timer A and determines the timer period service rate using the
following equation:
NCS is an integer between 1 and 8 that represents the number of enabled chip-selects that
select this UPM. The DFBRG field is the division factor for the BRGCLK, which can be
divided by 1 (default), 4, 16, or 64 and is programmed in the SCCR (described in
Section 5.2.1 System Clock and Reset Control Register).
For example, for DRAM to maintain data integrity an access or refresh must occur every
15.6µs. Use the equation above to determine the PTA value for UPMA to perform memory
refresh. Given that you have a 25MHz system clock with the required service rate of 15.6µs,
a periodic timer prescaler equal to 32, and a DFBRG field that is equal to 0, then the PTA
value must be (25 × 15.6) / (2
2×0
× 32× 1) = 12. If you want to perform more than one refresh
per service, use the TLFA field.
MAMR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
PTA PTAE AMA RES DSA RES
RESET
0 0 0 000
R/W
R/W R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x170
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
G0CLA
GPLA4
DIS
RLFA WLFA TLFA
RESET
01000
R/W
R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x172
Note: The UPM refresh is done in a round robin manner. If more than one chip-select
uses the same UPM, the refreshes will progress through each one. For example,
if you have three chip-selects using UPMA, you would need to set the periodic
timer A period to one-third the normal refresh.
PTA
System Clock (MHz) Service Duration (µs)×
2
2 DFBRG
×
Prescaler (PTP)× NCS×
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