LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
MOTOROLA
MPC823e REFERENCE MANUAL
xxxix
16-124.SPI Transfer Format If CP is Set to 0 ........................................................16-446
16-125.SPI Transfer Format If CP is Set to 1 ........................................................16-446
16-126.I
2
C Controller Block Diagram .....................................................................16-456
16-127.I
2
C Timing ..................................................................................................16-458
16-128.Byte Write to Device with Internal Addresses ............................................16-459
16-129.Byte Write to Device without Internal Addresses .......................................16-459
16-130.Byte Read from Device with Internal Addresses .......................................16-460
16-131.Byte Read from Device without Internal Addresses ..................................16-460
16-132.I
2
C Memory Format ...................................................................................16-467
16-133.Parallel Block Diagram For PA15 ..............................................................16-482
16-134.Parallel Block Diagram For PA14 ..............................................................16-483
16-135.MPC823e Interrupt Structure .....................................................................16-499
16-136.Interrupt Request Masking ........................................................................16-504
Section 17
PCMCIA Interface
17-1. System with One PCMCIA Socket .................................................................17-2
17-2. Internal DMA Request Logic ..........................................................................17-9
17-3. PCMCIA Single Beat Read Cycle (PRS = 0, PSST = 1, PSL = 3,
PSHT = 1) ....................................................................................................17-22
17-4. PCMCIA Single Beat Read Cycle (PRS = 0, PSST = 2, PSL = 4,
PSHT = 1) ....................................................................................................17-23
17-5. PCMCIA Single Beat Read Cycle (PRS = 0, PSST = 1, PSL = 3,
PSHT = 0) ....................................................................................................17-24
17-6. PCMCIA Single Beat Write Cycle (PRS = 2, PSST = 1, PSL = 3,
PSHT = 1) ....................................................................................................17-25
17-7. PCMCIA Single Beat Write Cycle (PRS = 3, PSST = 1, PSL = 4,
PSHT = 3) ....................................................................................................17-26
17-8. PCMCIA Single Beat Write with Wait (PRS = 3, PSST = 1, PSL = 3,
PSHT = 0) ....................................................................................................17-27
17-9. PCMCIA Single Beat Read with Wait (PRS = 3, PSST = 1, PSL = 3,
PSHT = 1) ....................................................................................................17-28
17-10. PCMCIA I/O Read of a 16-Bit Slave Port (PPS = 1, PRS = 3, PSST = 1,
PSL = 2, PSHT = 0) .....................................................................................17-29
17-11. PCMCIA I/O Read of an 8-Bit Slave Port (PPS = 1, PRS = 3, PSST = 1,
PSL = 2, PSHT = 0 .......................................................................................17-30
17-12. PCMCIA DMA Read Cycle (PRS = 4, PSST = 1, PSL = 3, PSHT = 0) ........17-31
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