Motorola MPC823e - Page 441

Memory Controller
MOTOROLA MPC823e REFERENCE MANUAL 15-83
MEMORY CONTROLLER
15
MEMORY CONTROLLER
15
Figure 15-47. Burst Write Access To Page Mode DRAM (Loop)
cst4 Bit 0 0 0 000
cst1 Bit 1 0
0 000
cst2 Bit 2 0
0 001
cst3 Bit 3 0
0 001
bst4 Bit 4 1
1 010
bst1 Bit 5 1
0 000
bst2 Bit 6 1
0 101
bst3 Bit 7 1
0 101
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t4 Bit 12
g1t3 Bit 13
g2t4 Bit 14
g2t3 Bit 15
g3t4 Bit 16
g3t3 Bit 17
g4t4 Bit 18
g4t3 Bit 19
g5t4 Bit 20
g5t3 Bit 21
- Bit 22
- Bit 23
loop Bit 24 0 1 100
exen Bit 25 0
0 100
amx0 Bit 26 0
0 001
amx1 Bit 27 0
0 000
na Bit 28 0
0 100
uta Bit 29 1
0 101
todt Bit 30 0
0 001
last Bit 31 0
0 001
WBS
WBS+1 WBS+2 WBS+3 WBS+4
CLKOUT/GCLK2
GCLK1
A[6:31]
TS
RD/ WR
D[0:31]
TA
CS1
BS_A [0:3]
ROW COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4
(
RAS )
(
CAS [0:3])