Motorola MPC823e - Page 5

TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MOTOROLA MPC823e REFERENCE MANUAL iii
6.2.2 Basic Instruction Pipeline ...........................................................6-4
6.3 Sequencer Unit .....................................................................................6-4
6.3.1 Flow Control ...............................................................................6-5
6.3.2 Issuing Instructions .....................................................................6-6
6.3.3 Interrupts ....................................................................................6-7
6.3.4 Implementing the Precise Exception Model ...............................6-8
6.3.4.1 Restartability After An Interrupt .....................................6-10
6.3.5 Processing an Interrupt ............................................................6-11
6.3.6 Serialization ..............................................................................6-12
6.3.6.1 Latency .........................................................................6-12
6.3.7 The External Interrupt ...............................................................6-13
6.3.7.1 Latency .........................................................................6-13
6.3.8 Interrupt Ordering .....................................................................6-14
6.4 The Register Unit ................................................................................6-15
6.4.1 Control Registers ......................................................................6-16
6.4.1.1 Physical Location of Special Registers .........................6-19
6.4.1.2 PowerPC Standard Control Register Bit Assignment....6-20
6.4.1.2.1 Machine State Register ....................................6-20
6.4.1.2.2 The Condition Register ....................................6-22
6.4.1.2.3 Fixed-Point Exception Cause Register ............6-23
6.4.1.3 Initializing the Control Registers ...................................6-24
6.4.1.3.1 System Reset Interrupt ....................................6-24
6.4.1.3.2 Hard/Soft Reset ................................................6-24
6.5 The Fixed-Point Unit ...........................................................................6-24
6.5.1 XER Update In Divide Instructions ...........................................6-24
6.6 The Load/Store Unit ............................................................................6-25
6.6.1 Issuing Load/Store Instructions ................................................6-26
6.6.2 Serializing Load/Store Instructions ...........................................6-27
6.6.3 Instructions Issued to the Data Cache .....................................6-27
6.6.4 Issuing Store Instruction Cycles ...............................................6-27
6.6.5 Issuing Nonspeculative Load Instructions ................................6-27
6.6.6 Executing Unaligned Instructions .............................................6-28
6.6.7 Little-Endian Mode Support ......................................................6-29
6.6.8 Atomic Update Primitives .........................................................6-29
6.6.9 Instruction Timing .....................................................................6-30
6.6.10 Stalling Storage Control Instructions ........................................6-30
6.6.11 Accessing Off-Core Special Registers .....................................6-30
6.6.12 Storage Control Instructions .....................................................6-31
6.6.13 Exceptions ................................................................................6-31
6.6.13.1 DAR, DSISR, and BAR Operation ................................6-31
Section 7