Introduction
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MPC823e REFERENCE MANUAL
MOTOROLA
INTRODUCTION
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• Data Bus Dynamic Bus Sizing for 8-,16-, and 32-Bit Buses
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Supports Traditional 68K Big-Endian, Traditional x86 Little-Endian, and PowerPC
Little-Endian Memory Systems
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Twenty-Six External Address Lines
• Completely Static Design (0–75MHz Operation)
• Communication Processor Module
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Embedded 32-Bit RISC Microcontroller Architecture for Flexible I/O
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Interfaces to PowerPC Core Through On-Chip 8K Dual-Access RAM and Virtual
(Serial) DMA Channels on a Dedicated DMA Accelerator
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Continuous Mode Transmission and Reception on All Serial and Parallel Channels
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Twenty Serial DMA (SDMA) Channels for Reception and Transmission on all Serial
and Parallel CPM Channels
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Programmable Memory-to-Memory and Memory-to-I/O (Including Flyby) DMA
Provided by Virtual DMA Support
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99MIPS @ 75MHz
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Protocols Supported by ROM or Download Microcode and the Hardware Serial
Communication Controllers Include, but are Not Limited to, the Digital Portions of:
— Ethernet/IEEE 802.3 (CS/CDMA)
— HDLC/SDLC and HDLC Bus
— Appletalk
— Signalling System #7 (RAM Microcode Option)
— Universal Asynchronous Receiver Transmitter (UART)
— Synchronous UART (USART)
— Totally Transparent Mode With/Without CRC
— Asynchronous HDLC
— IrDA Version 1.1 Serial Infrared (SCC2 only)
— Basic Rate ISDN (BRI) in Conjunction with Serial Management
Controller Channels
— V.38bis 33.6kbaud Modem
— Primary Rate ISDN
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16 x 16-Bit Multiply Accumulate (MAC) Hardware
— One Operation Per Clock
— Two Clock Latency and One Clock Blockage
— Operates Concurrently with Other Instructions
— Uses DMA Controller to Burst Data Directly into Register File without Interacting
with the PowerPC Core
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DSP Functions are Supported by ROM or Download Microcode and the
Communication Processor Module DSP Capabilities, Include but are No Limited to
JPEG Compression/Decompression
• Four Independent Baud Rate Generators and Two Input Clock Pins for Supplying
Clocks to the SCC and SMC Serial Channels