Communication Processor Module
MOTOROLA
MPC823e REFERENCE MANUAL
16-75
COMMUNICATION
16
PROCESSOR MODULE
TIMERS
16.4.2 Timer Operation
The clock input to the prescaler can be selected from three sources:
• The general system clock
• The general system clock divided by 16
• The corresponding TINx pin
The general system clock is generated in the clock synthesizer and defaults to the system
frequency (25 or 50MHz). However, the general system clock has the option to be divided
before it leaves the clock synthesizer. This mode, called normal low, is used to save power.
Whatever the resulting frequency of the general system clock, you can either choose that
frequency or the frequency divided by 16 as the input to the prescaler of each timer. On the
other hand, you may prefer that the TINx pin be the clock source because it is internally
synchronized to the internal clock.
The clock input source is selected by the ICLK field of the corresponding timer mode
register. The prescaler is programmed to divide the clock input by values between 1 and 256
and the output of the prescaler is used as an input to the 16-bit counter. The best resolution
of the timer is one clock cycle (40ns at 25MHz). The maximum period is 268,435,456 cycles,
which is 10.7 seconds at 25MHz. Both values assume that the general system clock is the
full 25MHz.
Each timer can be configured to count until a reference is reached and then either begin a
new time count immediately or continue running. The FRR bit of the corresponding timer
mode register selects each mode. When the reference value is reached, the corresponding
bit in the timer event register is set and an interrupt is issued if the ORI bit in the timer mode
register is set. Timers 1 and 2 can output a signal on the timer output pin (TOUT
1 and
TOU
T2) when the reference value is reached or selected by the OM bit of the corresponding
timer mode 1 or 2 register. This signal can be an active-low pulse or a toggle of the current
output. Timer 1 is exclusive-Or'ed with the SPKR
input signal to generate SPKROUT. This
allows the system to output simple frequencies for alerts. To prevent this timer from affecting
SPKROUT, choose one of the other timers or set this timer to a pulse mode.
In addition, each timer has a 16-bit timer capture register that is used to latch the value of
the counter when a defined transition of the TIN1, TIN2, TIN3, or TIN4 pin is sensed by the
corresponding input capture edge detector. The type of transition triggering the capture is
selected by the CE field in the corresponding timer mode register. When a capture or
reference event occurs, the corresponding bit in the timer event register is set and a
maskable interrupt request is issued to the CPM interrupt controller. Timers 1 and 2 can be
gated or restarted using the TGATE1
signal (timers 3 and 4 cannot be gated). Normal gate
mode enables the count on the falling edge of the TGATE1
pin and disables the count on
the rising edge of the TGATE1
pin. This mode allows the timer to count conditionally,
depending on the state of the TGATE1
pin.
TIMERS
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