Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-99
IDMA
COMMUNICATION
16
PROCESSOR MODULE
DFCR—Destination Function Code Register
The 8-bit destination function code register contains the value that you would like to appear
on the AT pins when the associated DMA channel accesses the destination memory. This
register also controls the byte-ordering convention used in transfers.
Bits 0–2—Reserved
These bits are reserved and must be set to 0.
BO—Byte Ordering
You must set this field to select the data buffer’s required byte ordering. If these bits
are modified on-the-fly, it takes effect at the beginning of the next frame or at the
beginning of the next buffer descriptor.
00 = The DEC/Intel convention is used for byte ordering (swapped operation). It is also
called little-endian byte ordering. The transmission order of bytes within a buffer
word is reversed in comparison to the Motorola mode. This mode can only be
used with 32-bit port size memory.
01 = PowerPC little-endian byte ordering. As data is transmitted onto the serial line
from the data buffer, the least-significant byte of the buffer double-word contains
data to be transmitted earlier than the most-significant byte of the same buffer
double-word.
1X = Motorola byte ordering (normal operation) is also called big-endian byte ordering.
As data is transmitted onto the serial line from the data buffer, the most-significant
byte of the buffer word contains data to be transmitted earlier than the
least-significant byte of the same buffer word.
ATx—Address Type 1–3
This field contains the function code value used during SDMA channel memory access.
AT0 is driven with a 1, so that this SDMA channel access is identified as a DMA-type
access.
DATA LENGTH
This field contains the number of bytes that IDMA must transfer to or from this buffer
descriptor data buffer. It must be programmed to a value greater than zero.
DFCR
BITS 0 1 2 3 4 5 6 7
FIELD RESERVED BO AT1 AT2 AT3
ADDR OFFSET + 2
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