Communication Processor Module
16-132 MPC823e REFERENCE MANUAL MOTOROLA
SERIAL
I/F
COMMUNICATION
16
PROCESSOR MODULE
TFSDx—Transmit Frame Sync Delay for TDMx
This field determines the number of clock delays between the transmit sync and the first bit
of the transmit frame.
00 = No bit delay. The first bit of the frame is transmitted/received on the same clock
as the sync.
01 = 1-bit delay.
10 = 2-bit delay.
11 = 3-bit delay.
Figure 16-52. Example of One Clock Delay from Sync to Data (RFSDx = 01)
Figure 16-53. Example of No Delay from Sync to Data (RFSDx = 00)
L1CLKx
L1SYNCx
DATA
(FE=1)
(CE=0)
BIT 0
ONE CLOCK DELAY FROM SYNC LATCH TO FIRST BIT OF FRAME
END OF FRAME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4
L1CLKx
L1SYNCx
DATA
BIT 0 BIT 1 BIT 2 BIT 3 BIT 0 BIT 1 BIT 2BIT 4
NO DELAY FROM SYNC LATCH TO FIRST BIT OF FRAME
(FE=1)
(CE=0)
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