Communication Processor Module
MOTOROLA
MPC823e REFERENCE MANUAL
16-153
SERIAL
I/F
COMMUNICATION
16
PROCESSOR MODULE
16.7.7.3 GCI INTERFACE PROGRAMMING EXAMPLE.
Assuming SCC2 is connected to
the D channel, SMC2 to the B1 channel, and SMC1 to the C/I channels, the initialization
sequence is as follows:
1. Program the serial interface RAM. Write all entries that are not used with 0x0001, set
the LST bit, and disable the routing function.
2. SIMODE = 0x0000c000. SCC2 is connected to the time-slot assigner. SCC2 supports
the grant mechanism since it is on the D channel.
3. The SICR equals 0x000040C0. SCC2 is connected to the time-slot assigner.
4. In the PAODR, bit 9 is set to 1. Configure L1TXDA to be an open-drain output.
5. In the PAPAR, bits 9, 8, and 7 are set to 1. Configure L1TXDA, L1RXDA, and
L1RCLKA.
6. In the PADIR, bits 9 and 8 are set to 1 and in the PADIR, bit 7 is set to 0. Configure
L1TXDA, L1RXDA, and L1RCLKA.
7. In the PCPAR, bit 4 is set to 1. Configure L1RSYNCA.
8. The SIGMR equals 0x04.Enable TDMA (one static TDM).
9. The SICMR is not used.
ENTRY
NUMBER
RAM WORD
SWTR SSEL CSEL CNT BYT LST DESCRIPTION
1 0 0000 110 0000 1 0 8 Bits SMC2 (B1)
2 0 0001 000 0000 1 0 Ext Device (B2)
3 0 0000 101 0000 1 0 8 Bits SMC1 (M)
4 0 0000 010 0001 0 0 2 Bits SCC2 (D)
5 0 0000 101 0101 0 0 6 Bits SMC1 (I+A+E)
6 0 0000 000 0110 1 0 Skip 7 Bytes
7 0 0000 000 0001 0 0 Skip 2 Bits
8 0 0000 111 0000 0 1 D Grant Bit
Note:
Since GCI requires the same routing for both receive and transmit, an exact
duplicate of the above entries must be written to both the receive and transmit
sections of the serial interface RAM beginning at addresses 0 and 128,
respectively.
Note:
If SCIT mode is not used, delete the last three entries of the serial interface RAM
and set the LST bit in the new last entry.
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